Low Power Carry Select Adder Design in VLSI Systems

Abstract

A digital circuit that performs addition is known as an electronic adder. Various numerical representations, including arithmetic and logical operations, can be used to create adders. Most adders work with binary numbers. The carry choose adder had the highest speed among the several adder types evaluated in this study. By employing the principles of the arithmetic logic unit (ALU), gate-level optimisation reduces the power consumption and area requirements of the carry selection adder. This study employed many methodologies, including the binary-to-excess converter (BEC) and Common Boolean Logic (CBL), to build the Carry Select Adder (CSLA). The comparative analysis indicates that the proposed ALU-based design consumes less power and has a smaller footprint than the conventional CSLA.