Reducing Latency in Network-on-Chip Using an Enhanced Mesh Topology

Abstract

This work presents a 2D Mesh-based topology with four extra lateral links, connected to eight special routes at the corners and the middle of the mesh. This work aims to reduce the network diameter by restricting the maximum hop count to N−1 in a regular N × N mesh. The proposed network is simulated using Dijkstra’s shortest-path routing algorithm, and it is found that lateral links are heavily used and incur average latencies of 10.662 and 11.869 cycles for N = 4 and N = 5, respectively. Also, the simulated results show a 56% reduction in maximum latency with the proposed topology for N = 5.