1.
Biswas A, Dhar S, Gupta YS, Paul A. Reducing Latency in Network-on-Chip Using an Enhanced Mesh Topology. DMP-LNCSE. 2026;(IMPACT26):535-547. Accessed March 29, 2026. https://digitalmanuscriptpedia.com/conferences/index.php/DMP-LNCSE/article/view/157